This project takes its first steps from the opportunity to put together the experience of the past years in the design of digital systems with dependability properties and the fast evolving research in the field of dynamic reconfiguration of FPGA devices. Soft Errors are radiation induced failures that cause the most problems in devices characterized by the presence of a relevant number of memory cells, whose content may be corrupted.

As a result, SRAM-based FPGAs, which are among the most interesting platforms for their flexibility and possibility to be “modified” at run time, are also the most sensible target platforms to such a class of faults. More precisely, since the configuration determining what functionality the device must perform is stored into SRAM memory, a Single Event Upset occurring in that memory will cause the system to misbehave, until a recovery process can be carried out. The project aims at exploiting the possibility to partially modify the system affected by a Single Event Upsets (SEU) fault in order to mitigate the effects of such failures and to recover its correct functionality. A description of the proposed framework is available here: framework.

An extension of the work to deal with permanent faults has been presented in [ETS2012] and to consider more complex systems needing bigger platforms has led to the design of dependable multi-FPGA architectures.

Fostered by the MEDIAN COST Action, the R4R methodology has been applied to a processor architecture, in a joint research activity with Prof. Psarakis, from the University of Piraeus. The first results are presented in [DFT2014A].

Representative publications related to this project:

• [DFT2014A]
  M. Psarakis, A. Vavousis, C. Bolchini and A. Miele, “Design and implementation of a Self-Healing Processor on SRAM-based FPGAs“, in Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, pp. 165-170, Oct 2014.
• [JETTA2013]
  C. Bolchini, A. Miele and D. Sandionigi, “Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms“, in Springer Journal of Electronic Testing, Vol. 29, No. 6, pp. 779-793, 2013, doi: http://dx.doi.org/10.1007/s10836-013-5418-4.
• [ETS2012]
  C. Bolchini, A. Miele and D. Sandionigi, “Increasing autonomous fault-tolerant FPGA-based systems’ lifetime“, in Proc. European Test Symposium (ETS), pp. 1-6, 2012, doi: http://dx.doi.org/10.1007/10.1109/ETS.2012.6233006.
• [TC2010]
  C. Bolchini, A. Miele and C. Sandionigi, “A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs,” in IEEE Trans. Computers, vol. 60, no. 12, pp. 1744-1758, December 2011, doi: 10.1109/TC.2010.281.
• [DFT2008]
  C. Bolchini and A. Miele, “Design Space Exploration for the Design of Reliable SRAM-based FPGA Systems,” Proc. IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 332-340, 2008, doi: 10.1109/DFT.2008.8.
• [DFT2007]
  C. Bolchini, A. Miele and M. D. Santambrogio, “TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs“, Proc. IEEE Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT), pp. 87-95, 2007, doi: 10.1109/DFT.2007.25.

A complete list of publications within this project by the group: link.

This work has been partially supported by MIUR PRIN-2008 project #2008K4P7X9.