Indeed, as hardened systems require many resources due to their size and complexity, a single FPGA may not suffice in terms of available resources, and multi-FPGA solutions become are therefore being taken into account and investigated. Furthermore, the availability of more devices on multi-FPGA platforms could be exploited to implement a distributed engine devoted to fault management. In fact, the use of multiple FPGAs provide an increased reliability as the overall functionality is spread over multiple devices, possibly also using redundant implementations.

While fault detection and masking techniques have been widely addressed in the case of systems based on a single FPGA, the problem extended to multi-FPGA platforms has been rarely taken into account. The multi-FPGA scenario arises various issues, for example the partitioning of the system among the available devices, and the single FPGA approaches can not be straightforwardly adopted. In literature, no complete design methodology handling all the peculiar issues of the considered scenario has been proposed yet, a gap we aim at filling with our work.

Relevant publications are:

• [DFT2011b]
  C. Bolchini and C. Sandionigi, “A reliability-aware partitioner for multi-FPGA platforms,” in Proc. IEEE Intl. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 34-40, Oct 2011
• [IOLTS2011]
  C. Bolchini, C. Sandionigi, L. Fossati and D. Merodio Codinachs, “A reliable fault classifier for dependable systems on SRAM-based FPGAs,” in Proc. IEEE Int. On-Line Testing Symposium (IOLTS), pp. 92-97, July 2011
• [ESL2010]
  C. Bolchini, C. Sandionigi, “Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation,” in IEEE Embedded Systems Letters Vol. 2, no. 4, pp. 107-110

This work has been partially supported by the European Space Agency, who co-funded Chiara Sandionigi’s PhD and by MIUR PRIN-2008 project #2008K4P7X9.