The trend of building new complex systems by integrating low-cost, inherently unreliable Commercial Off-The-Shelf (COTS) components is one of today\u2019s challenges in the design, analysis and development of systems exhibiting a certain degree of dependability. In fact, the last decade has seen the complexity of electronic systems growing faster and faster, thanks to the decrease of the components\u2019 size and cost. However, the use of low-cost execution resources to achieve high performance makes modern electronic devices more and more unreliable, because of the increasing susceptibility of such components to faults. In fact, the number of hard faults, as well as soft ones, is growing due mainly to the shrinking of components themselves, to the variations in the manufacturing process and to the exposition of devices to radiations and noise fluctuations.<\/p>\n
Therefore, when adopting the COTS-based design approach for the realization of modern and pervasive electronic systems, reliability<\/em> has become one of the main optimization goals, together with performance<\/em>. Nevertheless, in non-critical environments, reliability must be leveraged in order not to introduce too high costs, associated with not so stringent requirements; moreover, in many situations, the need for reliability may change during the activity depending on the specific working scenario. For these reasons, we claim that there is a need for a new way to dynamically “tune” fault management properties based on the working scenario, thus finding a satisfying trade-off between benefits and costs at run-time.<\/p>\n We have taken into account multicore and manycore architectures, working on the definition of run-time resource management strategies aimed at improving the system reliability while fulfilling performance constraints. The proposed solutions aim at mitigating soft errors as well as permanent one; moreover, we also tackle the issue of optimal resource exploitation in order to extend the system lifetime by mitigating wearout effects.<\/p>\n Recent publications:<\/p>\n This work partially fits under the umbrella of the EU COST Action IC1103 MEDIAN (website<\/a>), for which I am one of the five initial proponents, started in Dec. 2011 and running until Nov. 2015. The action fosters collaborations between participants by supporting short term scientific missions and other similar activities.<\/p>\n","protected":false},"excerpt":{"rendered":" The trend of building new complex systems by integrating low-cost, inherently unreliable Commercial Off-The-Shelf (COTS) components is one of today\u2019s challenges in the design, analysis and development of systems exhibiting a certain degree of dependability. In fact, the last decade has seen the complexity of electronic systems growing faster and faster, thanks to the decrease … Continue reading self-adaptive dependable systems<\/span> \n
A. Das, A. Kumar, B. Veeravalli, A. Miele,C. Bolchini, “An adaptive approach for online fault management in many-core architectures<\/span>,” in Proc. IEEE Design, Automation and Test in Europe, DATE, pp. 1429-1432, Mar. 2014, doi: http:\/\/dx.doi.org\/10.1109\/DATE.2012.6176589<\/a><\/li>\n
C. Bolchini, M. Carminati, A. Miele, “Self-Adaptive Fault Tolerance in Multi-\/Many-Core Systems<\/span>,” in Springer<\/em> Journal of Electronic Testing, Vol. 29, No. 2, pp. 159-175, Apr 2013, doi: http:\/\/dx.doi.org\/10.1007\/s10836-013-5367-y<\/a><\/li>\n
C. Bolchini, M. Carminati, A. Miele, A. Das, A. Kumar, B. Veeravalli, “Run-time mapping for reliable many-cores based on energy\/performance trade-offs<\/span>,” in Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, pp. 58-64, Oct 2013, doi: http:\/\/dx.doi.org\/10.1109\/DFT.2013.6653583<\/a><\/li>\n
C. Bolchini, A. Miele, D. Sciuto”An adaptive approach for online fault management in many-core architectures<\/span>,” in Proc. Design Automation & Test in Europe, DATE, pp. 1429-1432, Mar 2012, ee: http:\/\/ieeexplore.ieee.org\/xpl\/freeabs_all.jsp?arnumber=6176589<\/a><\/li>\n<\/ul>\n